1. Field of the Invention
This invention generally relates to integrated circuit devices, and more particularly to a field effect transistor with a sub-micron channel length, a lightly doped drain (LDD) structure, and an inverted T-gate interconnect region. The invention is also a method for making a device of this type.
2. Description of the Related Art
Various approaches have been taken to improve the performance of sub-micron, ultra-high-performance devices. One approach, disclosed in U.S. Pat. No. 5,817,558 to Wu, involves forming a T-gate field effect transistor from a lightly doped drain (LDD) structure. An LDD structure is a lightly doped buffer region typically located between a heavily doped drain region and a gate region. Functionally, LDD structures disperse the electric field of the channel and drain region. This, in turn, reduces electric field strength and, commensurately, the generation of high-energy particles, all of which reduce an undesirable phenomenon known as channel hot carrier effect.
Forming the LDD structure mentioned above involves doping low energy phosphorus ions (5xcx9c60 KeV) to form an N-region having a concentration of about 5xc3x971012xe2x88x923xc3x971015 ions/cm2. A recessed groove is then formed using dry etching techniques within the N-region to accommodate a T-shaped gate layer. In carrying out these steps, lithography is often employed to form various mask patterns for various elements of the device. This structure also uses spacers to reduce the effective channel length of the device.
Conventional T-gate field effect transistors using LDD structures have proven to have several drawbacks which adversely affect their performance. For example, the structure disclosed in U.S. Pat. No. 5,817,558 forms source/drain and LDD junctions after spacer and gate formation, which has proven to be inefficient and limiting of effective channel length. This method also involves etching a groove in the substrate which has also proven to be undesirable. Other conventional methods increase series resistance and thus reduce drive current and device performance.
In view of the foregoing considerations, it is clear that there is a need for a gate-controlled device which operates with improved performance compared with conventional devices, and a method for making such an improved device.
It is an object of the present invention to provide a gate-controlled device which operates with improved performance compared with conventional devices, and moreover one which realizes reduced series resistance and increased drive current without increasing gate-to-source/drain parasitic capacitance.
It is another object of the present invention to provide a method for forming the aforementioned gate-controlled device in the most effective and cost efficient manner possible.
The foregoing and other objects of the invention are achieved by providing a field effect transistor (FET) which includes a base layer, source/drain regions formed in the base layer, and an inverted-T gate layer between the source/drain regions, and shallow LDD extension regions in the base layer. The shallow LDD extension regions are formed in overlapping relationship with the gate layer, but the gate layer and the source/drain regions do not overlap. Furthermore, the shallow LDD extension regions are in contact with the inverted-T gate layer and the source/drain regions. The FET also includes spacers formed on the sides of the inverted-T gate layer. To form the inverted xe2x80x9cT,xe2x80x9d portions of the gate layer project underneath the spacers. Gate insulator layers are formed on the spacers, and CoSi silicide layers are formed on the source/drain regions and a top surface of the inverted-T gate layer.
The FET of the present invention outperforms conventional devices in a number of ways. First, the invention has lower external resistance than conventional devices achieved by providing a gate-controlled inversion channel over at least a portion of the shallow LDD extensions, and by making the shallow LDD extensions graded (or sloped) towards the deep source/drain regions. Also, by etching the gap regions underneath the spacers and then filling these regions with a gate oxide and poly gate interconnect, the invention is able to perform electrical gate control of the shallow LDD junctions. This advantageously reduces the series resistance of the device and increases drive current, both of which translate into improved device performance with no increase in gate-to-source/drain parasitic capacitance.
The FET of the present invention is also able to control overlap capacitance as a result of a hydrofluoric acid vapor etch, and more specifically by controlling the amount of hydrofluoric acid vapor used to perform the etch. The invention also realizes a shorter channel length, higher Idsat (drain current at saturation), and thus better overall performance.
The method for making the field effect transistor (FET) of the present invention includes implanting source/drain regions in a base layer, depositing a first doped oxide layer over the base layer, forming a masking layer over the first doped oxide layer, etching an opening in the first doped oxide layer and the masking layer to expose the base layer, forming a second doped oxide layer in the opening, depositing spacers along side walls of the opening and on top of the second doped oxide layer, and implanting shallow extension regions into the base layer using a light dopant. The shallow extension regions are formed to extend from the source/drain layers to underneath the opening.
The method further includes selectively etching gaps in the second doped oxide layer at a position underneath the spacers and above said lightly doped, shallow extension regions. The opening is then filled along with the gaps to form an inverted-T gate in overlapping relationship with the shallow extension regions, but not overlapping the source/drain regions. CoSi layers are then formed on the base layer over top the source/drain regions and gate.
In performing the method of the present invention, the deep source/drain regions and shallow extensions are completed before deposition of the gate insulator layers. This opens a route to high dielectric constant (k or ∈) dielectrics with reduced temperature stability. The method also controls the formation (length and location) of the shallow extensions independently of the self-aligned silicide locations. As a further advantage, channel implants for threshold voltage (Vt) adjustments may be made through a center of the opening using the so-called xe2x80x9cblob in the middlexe2x80x9d technique, which involves doping by implantation right under the gate. This is made possible by having an opening where the later-to-be-formed gate is going to be. This process may also be performed in a self-aligned manner, which allows for dopant dose reduction, separated from the deep source/drain junctions, resulting in reduced junction capacitance.